Products

PCIe and FPGA hardware product lines.

AuroraCore products target high-speed data acquisition, deterministic PCIe transfer, FPGA-based interface adaptation, and host-side integration.

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PX4-DMA PCIe acquisition card illustration

PX4-DMA Series

PCIe DMA Acquisition Card

PX4-DMA is a PCIe acquisition and streaming card family for systems that need direct high-throughput movement between external data sources, FPGA processing logic, and host memory.

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PCIe endpoint architecture for sustained host memory transfers
DMA pipeline design for streaming acquisition workloads
FPGA-side buffering, packetization, and flow-control logic
Host driver adaptation for application-level data access

FX1 Series

FPGA Interface Module

FX1 is a programmable FPGA interface module for bridging custom signals, board-to-board links, and device-specific communication protocols into a controlled host system.

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FPGA fabric for custom interface logic and protocol adaptation
Configurable data routing between device interfaces and PCIe
Timing-aware architecture for repeatable acquisition behavior
Integration support for host software and validation tools

LT-Link Series

Low-Latency PCIe Endpoint

LT-Link is a low-latency PCIe endpoint hardware line for command, telemetry, and control paths where predictable response time is more important than raw aggregate bandwidth alone.

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Low-overhead endpoint design for command and telemetry paths
Register, queue, and interrupt strategies tuned for host control
FPGA logic partitioning for deterministic transfer behavior
Driver and user-space interface adaptation for deployment

Specifications

Preliminary product specification table.

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Product Line	Host Interface	Target Throughput	Primary I/O	Integration Scope
PX4-DMA	PCIe Gen3 x4 endpoint	Up to 3.2 GB/s sustained DMA in reference validation	External acquisition, trigger, timing, FPGA fabric	Board configuration, DMA path, host driver adaptation
FX1	PCIe or board-to-board host bridge	Project-specific, interface dependent	GPIO, LVDS, SERDES, custom protocol lanes	FPGA logic, protocol bridge, timing validation
LT-Link	Low-latency PCIe endpoint	Command/telemetry optimized rather than bulk bandwidth	Register, queue, interrupt, control-plane links	Endpoint profile, user-space API, latency test utilities

Specifications are preliminary reference targets and may vary by FPGA device, board revision, operating system, and host platform.

Application 01

Scientific Acquisition

Multi-channel acquisition systems requiring deterministic host memory transfer, trigger alignment, and repeatable buffering behavior.

Application 02

Industrial Test

Production validation rigs that need FPGA-side protocol adaptation, low-latency command loops, and controlled host software access.

Application 03

Embedded Vision

Frame or packet movement from custom sensors into workstation-class hosts with predictable DMA scheduling and validation tooling.

Application 04

Telemetry Control

Command, telemetry, and status paths where bounded response time and reliable endpoint behavior matter more than peak throughput.